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2nd IEEE International GHz/Gbps Test Workshop (GTW’05)
November 10-11, 2005
Austin Convention Center
Austin, Texas, USA
Held in conjunction with International Test Conference/Test Week (TM)

http://www.unipi.gr/gtw

CALL FOR PAPERS

Scope -- Author Information -- Committees

Scope

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Chips running in the multi-GHz clock ranges and/or including I/O capable of multi-Gbps data rates
are now increasingly common. The characterization and production testing and diagnosis of such
chips pose significant challenges. Such chip and system trends are mirrored by new trends in ATE
and test methodologies. GTW’05 is a TTTC workshop that specifically focuses on problems and
solutions related to the test-related issues that arise with ICs running at such GHz clock and/or Gbps
data rates. GTW'05 will offer a focused forum for experts in the field, as well as for members of the
community with a particular interest in this rapidly expanding specialized field.

Areas of interest include but are not limited to:

  • Tester architecture and circuitry to provide and support high-speed analog signal sourcing/generation
    and response capture/sampling
  • Embedded and internal/external (hybrid) schemes and circuits for sourcing and capturing high speed
    signals
  • Low bandwidth testing/testers of GHz/Gbps circuits
  • Low-cost testing/testers of GHz/Gbps circuits
  • BIT/BIST for GHz/Gbps circuits
  • Jitter generation and analysis techniques, and circuitry using embedded, external, and hybrid circuitry
  • Driving and measuring specifications of I/Os with differential signaling
  • High-speed/multi-channel test problems and solutions (test fixturing, noise, signal integrity etc)
  • On-chip infrastructure IP for accurate on-chip timing, voltage, and current measurements
  • Noise modeling and characterization of channels, cabling, sources, receivers, etc.
  • Device interface circuitry, and tradeoffs in accuracy and bandwidth
  • Tradeoffs between yield, ATE overall timing accuracy (OTA), test environment specifications, and I/O
    timing specifications
  • DFT and design for manufacturing (DFM) of Gbit/s I/Os
  • High-speed I/O test power management
  • Test stimulus and response data transfer and processing, for go/no-go testing and diagnosis

Author Information

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To present at the workshop, authors are invited to submit paper proposals. The proposals may be
extended abstracts (1,000 words) or full papers. Each submission should include: title, full name and affiliation of all authors, an abstract of 50 words, and keywords. Also, identify a contact author and include a complete correspondence address, phone number, fax number, and e-mail address.

Submit a pdf version of your paper proposal via E-mail. Proposals for panel discussions are also
invited. Submissions are due no later than 20 August 2005.

Submit your paper/panel proposal(s) to Prof. David Keezer, Georgia Tech.,
david.keezer@gatech.ece.edu, Tel: +1-404-894-4741.

Authors will be notified of the disposition of their papers by 10 September 2005.

Authors of accepted papers may submit an illustrated text by 30 September 2005 for inclusion in the
Digest of Papers, which will be provided to the attendees.

For general information contact:

André Ivanov
U. of British Columbia
Tel: +1-604-822-6936
Fax: +1-604-822- 9506
E-mail: ivanov@ece.ubc.ca

Committees

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General Co-Chairs
A. Ivanov, U. of British Columbia
A. Chatterjee, Georgia Tech.

Program Chair
D. Keezer, Georgia Tech.

Publicity
D. Gizopoulos, U. Piraeus

Finance Chair
S. Tabatabaei, Virage Logic

Publications Chair
M. Lubaszewski, UFRGS/IMSE

PROGRAM COMMITTEE (to include):

K. Arabi, PMC-Sierra
R. Aitken, Artisan
Y. Cai, Agere
T. Cheng, UCSB
A. Crouch, Inovys
J. Figueras, U. Politecnic Catalunya
C. Force, Texas Instruments
W. Maichen, Teradyne
W. Mann, SWTW
A. Meixner, Intel
M. Li, Wavecrest
S.-I. Liu, National Taiwan U.
S. Ozev, Duke U.
G. Roberts, McGill U.
M. Slamani, IBM
M. Soma, U. Washington
T. Yamaguchi, Advantest
J. A. Abraham, UT Austin
H. Haggag, National Semiconductor
W. R. Eisenstadt, U. Florida
M. A. d’Abreu, Sun Microsystems

For more information, visit us on the web at: http://www.unipi.gr/gtw

The 2nd IEEE International GHz/Gbps Test Workshop (GTW’05) is sponsored by the Institute of Electrical and Electronics Engineers (IEEE) Computer Society's Test Technology Technical Council (TTTC).


IEEE Computer Society– Test Technology Technical Council

TTTC CHAIR
André IVANOV
University of British Columbia– Canada
Tel. +1-604-822-6936
E-mail ivanov@ece.ubc.ca

SENIOR PAST CHAIR
Yervant ZORIAN
Virage Logic– USA
Tel. +1-510-360-8035
E-mail yervant.zorian@viragelogic.com


TTTC 2ND VICE CHAIR
Michel RENOVELL
LIRMM– France
Tel. +33 467 418 523
E-mail renovell@lirmm.fr

FINANCE CHAIR
Adit D. SINGH
Auburn University– USA
Tel. +1-334-844-1847
E-mail adsingh@eng.auburn.edu

IEEE DESIGN & TEST EIC
Rajesh K. GUPTA
University of California, Irvine– USA
Tel. +1-949-824-8052
E-mail gupta@uci.edu

TECHNICAL MEETINGS
Cheng-Wen WU

National Tsing Hua Univ.– Taiwan
Tel. +886-3-573-1154
E-mail cww@computer.org

TECHNICAL ACTIVITIES
Victor Hugo CHAMPAC
Instituto Nacional de Astrofisica– Mexico
Tel.+52-22-470-517
E-mail champac@inaoep.mx

ASIA & SOUTH PACIFIC
Hideo FUJIWARA
Nara Inst. of Science and Technology– Japan
Tel. +81-74-372-5220
E-mail fujiwara@is.aist-nara.ac.jp

LATIN AMERICA
Marcelo LUBASZEWSKI
Federal Univ. of Rio Grande do Sul (UFRGS)– Brazil
Tel. +34-93-401-6603
E-mail luba@vortex.ufrgs.br

NORTH AMERICA
William R. MANN
Tel. +1-949-645-3294
E-mail william.mann@ieee.org

COMMUNICATIONS
Adit D. SINGH
Auburn University– USA
Tel. +1-334-844-1847
E-mail adsingh@eng.auburn.edu

INDUSTRY ADVISORY BOARD
Yervant ZORIAN
Virage Logic, Inc.– USA
Tel. +1-510-360-8035
E-mail yervant.zorian@viragelogic.com

 

PAST CHAIR
Paolo PRINETTO
Politecnico di Torino– Italy
Tel. +39-011-564-7007
E-mail Paolo.Prinetto@polito.it

TTTC 1ST VICE CHAIR
Adit D. SINGH
Auburn University– USA
Tel. +1-334-844-1847
E-mail adsingh@eng.auburn.edu

SECRETARY
Christian LANDRAULT
LIRMM– France
Tel. +33-4-674-18524
E-mail landrault@lirmm.fr

ITC GENERAL CHAIR
Rob AITKEN
Artisan Components– USA
Tel. +1-408-548-3297
E-mail aitken@artisan.com

TEST WEEK COORDINATOR
Yervant ZORIAN
Virage Logic, Inc.– USA
Tel. +1-510-360-8035
E-mail yervant.zorian@viragelogic.com

TUTORIALS AND EDUCATION
Dimitris GIZOPOULOS

Univ. of Piraeus– Greece
Tel. +30-210-414-2372
E-mail dgizop@unipi.gr

STANDARDS
Rohit KAPUR

Synopsys– USA
Tel. +1-650-934-1487
E-mail rkapur@synopsys.com

EUROPE
Joan FIGUERAS
Univ. Politècnica de Catalunya– Spain
Tel. +55-51-228-1633, Ext. 4830
E-mail figueras@eel.upc.es

MIDDLE EAST & AFRICA
Ibrahim HAJJ
American University of Beirut– Lebanon
Tel. +961-1-341-952
E-mail ihajj@aub.edu.lb

STANDING COMMITTEES
Michael NICOLAIDIS
iRoC Technologies– Greece
Tel. +33-4-381-20763
E-mail michael.nicolaidis@iroctech.com

ELECTRONIC MEDIA
Alfredo BENSO
Politecnico di Torino– Italy
Tel. +39-011-564-7080
E-mail alfredo.benso@polito.it


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